Hardware Lockstep Core Execution: Redundant Arithmetic Units, Comparator Logic & Delay Staggering

Radiation-induced single-event upsets (SEUs) and silicon crosstalk can flip bits inside CPU registers, causing calculation errors in steering or braking logic.

In a Dual-Core Lockstep (DCLS) architecture: • Two identical CPU cores execute the exact same instruction stream. • The redundant checker core is delayed by 2 clock cycles (temporal staggering) and physically rotated 90 degrees on the silicon die (spatial diversity) to prevent identical common-cause disturbances. • Hardware comparator logic continuously verifies core outputs on every clock cycle. If a single-bit discrepancy occurs, the comparator asserts an instantaneous non-maskable safety interrupt within one clock cycle, safely transitioning the system before corrupted data can reach vehicle actuators.